Veriloggen

- python 2.7.9 + pyverilog 1.0.0
- python 3.4.2 + pyverilog 1.0.0

Update
====

- Added `stream.RandXorshift` for pseudo random number generators.
- To improve the clock frequency, skid buffers are introduced to the AXI data transfer units.
- `thread` supports `f-strings`

This version is suitable for NNgen 1.3.4.

Test environment
====

macOS 13.5.2 (Apple Silicon M2 Max)
----

Python 3.10.6

- Icarus Verilog 12.0
- Pyverilog 1.3.0
- numpy 1.26.0rc1
- Jinja2 3.1.2

Ubuntu 20.04.6 (AMD Ryzen 9 5950X)
---

Python 3.10.6

- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy 1.26.0rc1
- Jinja2 3.1.2

Update
====

- Added right-first operators (such as `__radd__`)
- Changed output file names to avoid name conflicts
- Added `ExtRAM` and `ExtFIFO` for implementing only RAM/FIFO interfaces connected to actual external RAM/FIFO objects.
- Bug fix of going through `dma_wait_write` when `AWREADY` is asserted after the `WREADY` is asserted in AXIM (AXI Master).

Test environment
====

macOS 13.2.1 (Apple Silicon M1 Max)
----

Python 3.10.6

- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy 1.24.2
- Jinja2 3.1.2

Ubuntu 20.04.5 (AMD Ryzen 9 5950X)
---

Python 3.10.6

- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy 1.24.2
- Jinja2 3.1.2

Update
====

- Bug fix of resolver especially for `generate` statements.
- resolver.resolve returns optimized modules after the deep-copy of the input modules.
- Updated AXIM to support python-native literal values as the transfer size.

Test environment
====

macOS 12.6.1 (Apple Silicon M2)
----

Python 3.10.6

- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy 1.23.2
- Jinja2 3.1.2

Ubuntu 20.04.5 (AMD Ryzen 9 5950X)
---

Python 3.10.6

- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy 1.23.4
- Jinja2 3.1.2

Update
====

- Improved the DMA transfer performance of `AXIM` by supporting multiple in-flight transactions. DMA request FIFOs are introduced.
- Introduced `dma_read_packed` and `dma_write_packed` for packed DMA transfers by MultibankRAM. The behavior is same as the `dma_read` and `dma_write` of MultibankRAM in the previous version, but the addressing mode is different.
- Changed the addressing granularity of DMA transfers for MultibankRAM.
- Implemented `dma_read_bcast` that broadcast a value to multiple RAMs.
- Reimplemented the burst read/write methods of RAM without the obsoleted `dataflow` classes. Old `dataflow` related methods are removed.
- `AxiMemoryModel` supports multiple in-flight transactions. Old `AxiMemoryModel` is renamed as `AxiSerialMemoryModel`.
- Removed `AXIM2`.
- Bug fix of multiple driver in stream.Substream.
- Added some actual examples running on Ultra96V2 with generated RTL source codes and synthesized bitstreams.

This version is suitable for NNgen 1.3.3.

Test environment
====

macOS 12.3.1 (Apple Silicon M1 Max)
----

Python 3.9.5

- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy 1.22.1
- Jinja2 3.0.3

Ubuntu 20.04.4 (AMD Ryzen 9 5950X)
---

Python 3.9.5

- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy 1.22.1
- Jinja2 3.0.3

Python 3.7.7

- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy 1.21.5
- Jinja2 3.0.3

Update
====

- Added `_set_***` methods without calling the tail goto_next() method.

Test environment
====

macOS 11.5 (Apple Silicon M1)
----

- Python 3.9.5
- Icarus Verilog 11.0
- Pyverilog 1.3.0
- numpy: 1.20.3

Ubuntu 20.04.2 (AMD Ryzen 9 5950X)
---

- Python 3.7.7 / 3.9.5
- Icarus Verilog 10.3
- Pyverilog 1.3.0
- numpy: 1.20.3