Veriloggen

Latest version: v2.3.0

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0.5.1

Update
- from_verilog: functions for reading existing Verilog code are improved.
- lib.dataflow supports user-custom operators by acc_custom().
- IntX and IntZ are merged to Int.
- More prettified source code is available with Pyverilog 1.0.2.

Test environment

0.5.0

Update
- Python 3.5.0 is supported, which is tested only on Mac OS environment.
- lib.dataflow is a dataflow pipeline builder (which is renamed from lib.pipeline).
- lib.dataflow supports the visualization by using pygraphviz (for python 2.7 and 3).
- lib.fsm: state traversal codes are evaluated and inserted lazily.
- lib.simulation supports ModelSim in addition to Icarus Verilog.
- Module supports add_hook(method, args, kwargs) for adding a lazy-evaluated method which is executed when to_verilog() method is called. Those methods do not affect the Module object state (like immutable), excepting the generated code. Usually a make_always() method is passed to add_hook(), and then it will called when to_verilog() is called.
- Constructor methods of lib.fsm.FSM, lib.seq.Seq, lib.dataflow.Dataflow are changed, so that they require a clock and reset signal. In contrast, make_always() methods do not require them no longer.
- All example codes use absolute_import and print_function for better Python3 support.

Test environment

0.4.3

Update
- lib.simulation.Simulator is for launching simulator from python directly.

Test environment

0.4.2

Update
- lib.parallel.Parallel -> lib.seq.Seq
- Import path description is updated, and unnecessary 'sys.path.insert's are removed.

Test environment

0.4.1

Update
- Very stable release.
- setup.py is updated for the library dependency.
- veriloggen/utils is moved to top-level.
- Directory hierarchy of 'sample' and 'tests' are updated.
- Acceleration of test

Test environment

0.4.0

- lib.Pipeline: a library for computation pipeline modeling as a dataflow is added.
- lib.FSM and lib.FSM: supporting prev() method to access the previous value of a reg.
- lib.Simulation: finish() method is added.
- to_verilog: number representation bugs are fixed.
- vtypes: IntX and IntZ are added. Object dump method __str__() is implemented for easy debugging. Type check capability is enhanced.

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