Veriloggen

- Better source code for both Python2.7 and Python3.4
- Some Verilog features are supported: initial, event, wait, system task, ...
- Some missing but basic operators are implemented.
- A feature for importing Verilog code is upgraded.
- New useful libraries: lib.parallel and lib.simulation
- Library update: lib.fsm
- A lot of examples are added and updated

- Two basic libraries (lib_fsm and lib_bundle)
- Almost basic syntaxes in Verilog HDL are supported
- type_check capability
- Supporting to import existing Verilog HDL source codes by using from_verilog
- Generate statement support
- Some new examples

- Test code by using Pytest
- FSM library (lib.FSM) is updated
- Bit selection ([X:Y], [X]) operation is supported
- Bit concatenation (Cat) is supported
- Explicit function statement generation is supported

More Verilog-like description style is supported.

First public release.