Veriloggen

Update
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- Changed the default values of AxCACHE, AxPROT, and AxUSER in AXI interfaces (veriloggen.types.axi, veriloggen.thread)

Test environment
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Update
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- Improvement of Fixed-Point (veriloggen.types.fixed, veriloggen.stream, veriloggen.thread)
- Added intermediate buffer operators: RingBuffer and Scratchpad (veriloggen.stream)
- Improvement of graph visualizer using pygraphviz (veriloggen.stream)
- Added reinterpret cast operator (veriloggen.stream)
- Added Split operator for SIMD-like processing (veriloggen.stream)
- Changed the default bit-width of AWUSER and ARUSER in AXI interfaces (veriloggen.types.axi, veriloggen.thread)

Test environment
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Update
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- Bug fix of Repeat operator (veriloggen.core)
- Bug fix of Shift-Right-Arithmetically operator (veriloggen.thread)
- Windows support (veriloggen.simulation)
- All of AXI interface signals are implemented in the AXI-based controllers. To create a complete AXI interface and IP-XACT, IPgen is no longer required. So IPgen is removed from the installation requirements.
- Updated the license description
- Added the contribution guideline

Test environment
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Update
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- Complement2, Abs, and Sign are implemented in veriloggen.core and stream.

Test environment
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Update
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- RAM style attribute is supported.

Test environment
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Update
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- A bug fix of fixed point.
- \_\_div\_\_ and \_\_truediv\_\_ in Thread compiler are swapped.

Test environment
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