Fusesoc

======================================================
* Use git-apply to avoid calling external patch command
* Use VLNV identifiers for cores
* Improved dependency handling using simplesat solver
* Allow loading core libraries from env var FUSESOC_CORES
* Add list-paths command
* Allow setting vlog `define from command-line
* Add Vivado backend
* Improve windows compatibility for modelsim and quartus
* Allow loading tclSource files in quartus
* Require valid file types for filesets
* Improve formatting of documentation for github
* Improved documentation
* Add option to setup EDA project without running build
* Add support for multiple top-level testbenches
* Make .system files optional
* Dropped support for Python 3.2 and 3.3
* Improved flow for Modelsim simulations
* Add Riviera Pro simulator support
* Add new standard core library to eventually replace orpsoc-cores
* Added tutorial for creating cores
* + improved error handling, bug fixes and refactoring

Contributors:
Antony Pavlov <antonynpavlovgmail.com>
Olof Kindgren <olof.kindgrengmail.com>
Philipp Wagner <philipp.wagnertum.de>
Stefan Wallentowitz <stefanwallentowitz.de>

======================================================
* Improve plusargs handling
* Fix core-info for verilator sections
* Allow multiple top-level modules in Icarus
* Fix VHDL and SystemVerilog support in ISIM
* Add support for the GHDL simulator
* Add support for Vivado Logicore cores
* Add support for ISE CoreGen cores
* Support IP-XACT 2009 and 2014 versions
* Add icestorm backend
* Allow settings default values for parameters
* Add support for Altera qip files
* Add CI testing with Travis and appveyor
* Experimental Windows support
* Allow Modelsim to run user TCL files
* Parallelize verilator jobs to speed up compilation
* + improved error handling, bug fixes and refactoring

Contributors:
Andrzej Radecki <ndrwrdckgmail.com>
Neil Turley <neilpturleygmail.com>
Olof Kindgren <olof.kindgrengmail.com>
Philipp Wagner <philipp.wagnertum.de>
Stefan Wallentowitz <stefanwallentowitz.de>

======================================================
* Allow setting top-level parameters in backends
* Allow FuseSoC to handle verilator CLI arguments
* Parse command-line before building sim model
* Support plusargs in XSIM
* Initial IP-Xact support (FileSets and description)
* Add distutils-based build system and add to pypi
* Support mixed-language (VHDL, verilog, SV) in ModelSim
* Support mixed-language (VHDL, verilog, SV) in XSIM
* Add fileset sections (replaces vhdl/verilog sections)
* Allow per-file attributes in .core
* + improved error handlig, bug fixes and refactoring

Contributors:
Chris Higgs <chris.higgspotentialventures.com>
Franck Jullien <franck.julliengmail.com>
Olof Kindgren <olof.kindgrengmail.com>

======================================================
* Add item to .core files to explicitly apply patches
* Export FuseSoC dirs as env vars to external commands
* Use relative paths everywhere
* Always rebuild sim model, except when --keep is used
* Prettify core-info output
* Generate CAPI directly from section.py
* Add more helpful data types to section members
* Support multiple top-level testbenches
* Add git provider
* Add pgm option to ISE backend
* Add support for Xilinx ISIM Simulator
* Abort FuseSoC on scripts with non-zero return code
* Run scripts from all core deps in simulations
* Add parameter section (replaces plusargs)
* Add support for Xilinx XSIM Simulator
* + improved error handling, bug fixes and refactoring

Contributors:
Andrzej Radecki <ndrwrdckgmail.com>
Franck Jullien <franck.julliengmail.com>
Jeffrey Esquivel S <jeffestudiomanati.com>
Leonardo Lessa <llessausers.noreply.github.com>
Lukas Rinderer <lukasgastro-plan.at>
Michael Gielda <mgieldaantmicro.com>
Olof Kindgren <olof.kindgrengmail.com>

======================================================
* Allow files in core root to overlay files in cache
* Add support for pre_build_scripts in cores
* Fix checks for SystemC environment variables
* Allow absolute file paths in core files
* Add --verbose flag for detailed output
* Add --monochrome flag for monochrome output
* Report all sections in core-info
* Allow cores to specify themselves as non-cachable
* Allow symlinks in core libraries
* Add update command to update core libraries
* Add init command for initial setup of core libraries
* Remove deprecated --systems-root flag
* Add configure flag to optionally disable SVN providers
* Allow cores to be located anywhere in the core libraries
* Add 32/64-bit autodetection with override
* Add git submodule provider
* Generate detailed ISE map report
* + improved error handling, bug fixes and refactoring

Contributors:
Christian Svensson <bluecmd.nu>
Franck Jullien <franck.julliengmail.com>
Jeremy Bennett <jeremy.bennettembecosm.com>
Olof Kindgren <olof.kindgrengmail.com>
Stefan Kristiansson <stefan.kristianssonsaunalahti.fi>

======================================================
* Support system-installed Verilator
* Allow tool-specific dependencies
* Allow custom names on synthesis/simulator top levels
* Allow subdirectories in cores_root
* Colorized status output
* Improved exception handling
* Allow verilator test benches to access functions in other cores
* Allow passing options directly to backend tools
* Add preliminary VHDL support
* Integrate Altera Qsys generation in Quartus flow
* Add support for building with Xilinx ISE
* + lots of bug fixes and refactoring

Contributors:
carlos <carlosmarte.inesc-id.pt>
Franck Jullien <franck.julliengmail.com>
Olof Kindgren <olof.kindgrengmail.com>
Stefan Kristiansson <stefan.kristianssonsaunalahti.fi>
Kenneth Lorthioir <ibelimbgmail.com>
Jose T. de Sousa <jtsinesc-id.pt>